*******************************************
#DFT script
#####################
# DFT part
#####################
read_verilog CPU_syn.vg
current_design CPU_TOP
current_design CPU_TOP
compile -scan high
source ./constrain.tcl
report_constraint -all_violators
#####################
# Link design
#####################
link
check_design
#####################
# Pre-Scan Area/Timing/Power report
#####################
report_area > cpu_ori.area_rpt
report_timing > cpu_ori.timing_rpt
report_power > cpu_ori.power_rpt
#####################
# Set test timing
#####################
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
set test_default_period 100
#####################
# Select scan style
#####################
set test_default_scan_style multiplexed_flip_flop
set_scan_configuration -create_dedicated_scan_out_ports true
set test_dedicated_subdesign_scan_outs true
set_fix_multiple_port_nets -all -buffer_constants -feedthroughs
set verilogout_no_tri 1
set write_name_nets_same_as_ports 1
####################
# Create test protocol
####################
set_dft_signal -view existing_dft -type ScanClock -port clk \
-timing [list 45 55]
set_dft_signal -view existing_dft -type reset -port rst \
-active_state 1
set_scan_configuration -create_dedicated_scan_out_ports true
set test_dedicated_subdesign_scan_outs true
set_fix_multiple_port_nets -all -buffer_constants -feedthroughs
set verilogout_no_tri 1
set write_name_nets_same_as_ports 1
create_test_protocol
####################
# Report design constraint violations
#####################
report_constraint -all_violators
####################
# Pre-scan test design rule checking
####################
dft_drc
####################
# Set scan architecture
####################
set_scan_configuration -chain_count 4
#####################
# Preview scan chain
#####################
preview_dft
#####################
# Build scan chain
#####################
insert_dft
####################
# Report design constraint violations
####################
report_constraint -all_violators
####################
# Post-scan test design rule checking
####################
dft_drc
####################
# Report scan
####################
report_scan_path -view existing -chain all > CPU.scan_path
report_scan_path -view existing -cell all > CPU.scan_cell
####################
# Post-Scan Area/Timing/Power report
####################
report_area > CPU_dft.area_rpt
report_timing > CPU_dft.timing_rpt
report_power > CPU_dft.power_rpt
####################
# Write test protocol
####################
write_test_protocol -output CPU_dft.spf
####################
# Write design
####################
set_fix_multiple_port_nets -all -buffer_constants -feedthroughs
set verilogout_no_tri 1
set write_name_nets_same_as_ports 1
write -hierarchy -format verilog -output CPU_dft.vg
write -hierarchy -format ddc -output CPU_dft.ddc
####################
# Write SDF file
####################
write_sdf -version 2.1 -context verilog CPU_dft.sdf
##constrain
create_clock -name "clk" -period 20 -waveform {"0" "10"} {"clk"}
set_dont_touch_network [ find clock clk]
set_fix_hold clk
set_operating_conditions "typical" -library "typical"
set_wire_load_model -name "ForQA" -library "typical"
set_wire_load_mode "segmented"
set_input_delay -clock clk 2 interrupt
set_input_delay -clock clk 2 rst
set_input_delay -clock clk 2 instr_IF[*]
set_input_delay -clock clk 2 MEMdata_MEM[*]
set_output_delay -clock clk 2 PCout[*]
set_output_delay -clock clk 2 memWrite
set_output_delay -clock clk 2 memRead
set_output_delay -clock clk 2 ALUresult_MEM[*]
set_output_delay -clock clk 2 data2_MEM[*]
set_max_area 0
set_max_fanout 8 CPU_TOP
set_max_transition 1 CPU_TOP
set_load 0.05 [get_ports "interrupt"]
set_load 0.05 [get_ports "rst"]
set_load 0.05 [get_ports "instr_IF[*]"]
set_load 0.05 [all_outputs]
