Script for Design Vision:
#####################
#Synthesis part
#####################
read_file -format verilog {/home/raid2_2/user99/r99079/final/CPU_TOP.v}
#####################
#Set Constraints
#####################
current_design CPU_TOP
create_clock -name "clk" -period 20 -waveform {"0" "10"} {"clk"}
set_dont_touch_network [ find clock clk]
set_fix_hold clk
set_operating_conditions "typical" -library "typical"
set_wire_load_model -name "ForQA" -library "typical"
set_wire_load_mode "segmented"
####################
set_input_delay -clock clk 2 interrupt
set_input_delay -clock clk 2 rst
set_input_delay -clock clk 2 instr_IF[*]
set_input_delay -clock clk 2 MEMdata_MEM[*]
set_output_delay -clock clk 2 PCout[*]
set_output_delay -clock clk 2 memWrite
set_output_delay -clock clk 2 memRead
set_output_delay -clock clk 2 ALUresult_MEM[*]
set_output_delay -clock clk 2 data2_MEM[*]
####################
set_max_area 0
set_max_fanout 8 CPU_TOP
set_max_transition 1 CPU_TOP
set_load 0.05 [get_ports "interrupt"]
set_load 0.05 [get_ports "rst"]
set_load 0.05 [get_ports "instr_IF[*]"]
set_load 0.05 [all_outputs]
# Remove unconnecting wire
set sh_enable_line_editing true
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
#####################
# Compile Desin
#####################
uplevel #0 check_design
compile -map_effort high
#####################
# Report timing, area
# and power
#####################
uplevel #0 { report_clock -nosplit }
uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group }
uplevel #0 { report_power -analysis_effort low }
uplevel #0 { report_area -nosplit }
# Remove assign
remove_unconnected_ports -blast_buses [get_cells * -hier]
set bus_inference_style {%s[%d]}
set bus_naming_style {%s[%d]}
set hdlout_internal_busses true
change_names -hierarchy -rule verilog
define_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type net
define_name_rules name_rule -map {{"\\*cell\\*" "cell"}}
change_names -hierarchy -rules name_rule
#####################
# Save gate level
# verilog file and sdf file
#####################
write -hierarchy -format ddc
write -hierarchy -format verilog -output /home/raid2_2/user99/r99079/final/CPU_syn.vg
write_sdf -version 2.1 /home/raid2_2/user99/r99079/final/CPU_syn.sdf
write_sdc CPU.sdc
######### End of Synthesis part ##########
